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precision analog front end and controller for battery test/formation systems data sheet AD8450 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features integrated constant current and voltage mode s with automatic switchover charge and d ischarge modes precision voltage and current measurement integrated precision control feedback blocks precision interface to pwm or linear power con verters programmable gain settings current sense gains: 26 , 66, 133, and 200 voltage sense gains: 0.2, 0.27, 0.4, and 0.8 programmable ovp and ocp fault detection current sharing and balancing e xcellent ac and dc p erformance m aximum offset voltage drift : 0.6 v/c m aximum gain drift : 3 ppm/c low current sense amplifier input voltage noise : 9 nv/ hz current sense cmrr: 126 db minimum ( gain = 200) ttl c ompliant l ogic applications battery cell formation and testing battery module testing general description t he AD8450 is a precision analog front end and controller for testing and monitoring battery cells . a p recision programmable gain instrumentation amplifier (pgia) measure s the battery charge/discharge current , and a programmable gain difference amplifier (pgda) measures the battery voltage (see figure 1 ). internal l aser trimmed resistor networks set the gains for the pgia and the pgda, optimiz ing the performance of the AD8450 over t he rated temperature range . pgia gain s are 26, 66, 133, and 200. pgda gains are 0.2, 0.27, 0.4, and 0.8. voltages at the iset and vset inputs set the desired constant current (c c ) and constant voltage (c v ) values. cc to cv sw i tching i s automatic and transp arent to the system. a ttl logic level input , mode, selects the c harge or discharge mode ( high for charge , low for discharge ) . a n analog output , vctrl, interfaces directly with the analog devices, inc., adp1972 pwm controller . the AD8450 includes resistor programmable overvoltage and over current dete ction and current sharing ci rcuitr y. current sharing is used to balance the output current of multiple bridged channels. th e AD8450 simplifies designs by providing excellent accuracy, performance over temperature, flexibility with fu nctionality, and overall reliability in a space - saving package. the AD8450 is available in an 80 - lead , 14 mm 14 mm 1 mm lqfp package and is rated for an operating temperature of ?40c to +85c . functional block diagram current sense pgia voltage sense pgda ismea iset bvmea vset vint fault isvn isvp bvnx bvpx vint vctrl 1 mode AD8450 ive0/ ive1 vve0/ vve1 ovps/ ovpr ocps/ ocpr imax csh vvp0 vsetbf vclp vcln bvrefh/ bvrefl isrefh/ isrefl vref current sharing voltage reference fault detection constant voltage loop filter constant current loop filter (charge/ discharge) switching gain network and mux gain network 26, 66, 133, 200 0.2, 0.27, 0.4, 0.8 1 1966-001 figure 1.
AD8450* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? AD8450 evaluation board documentation application notes ? an-1319: compensator design for a battery charge/ discharge unit using the AD8450 or the ad8451 data sheet ? AD8450: precision analog front end and controller for battery test/formation systems data sheet user guides ? ug-845: AD8450/adp1972 battery testing and formation evaluation board tools and simulations ? AD8450 spice macro model reference materials press ? analog devices introduces the first integrated analog controller optimizing high-efficiency rechargeable battery manufacturing design resources ? AD8450 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD8450 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
AD8450 data sheet rev. b | page 2 of 41 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revi sion history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 pgia characteristics ................................................................. 11 pgda cha racteristics ................................................................ 13 cc and cv loop filter amplifiers, uncommitted op amp, and vset buffer ......................................................................... 15 vint buffer ................................................................................ 17 current sharing amplifier ........................................................ 18 co mparators ................................................................................ 19 reference characteristics .......................................................... 20 theory of operation ...................................................................... 21 introduction ................................................................................ 21 programmable gai n instrumentation amplifier (pgia) ..... 23 programmable gain difference amplifier (pgda) .............. 24 cc and cv loop filter amplifiers .......................................... 24 compensation ............................................................................. 26 vint buffer ................................................................................ 26 mode pin, charge and discharge control ........................... 26 overcurrent and overvoltage comparators ........................... 27 current sharing bus and imax output ................................. 28 applications information .............................................................. 29 functional description .............................................................. 29 power supply connections ....................................................... 29 power supply sequencing ......................................................... 29 powe r - on sequence ................................................................... 29 power - off sequence ................................................................... 30 pgia connections ..................................................................... 30 pgda connections ................................................................... 31 battery curr ent and voltage control inputs (iset and vset) ....................................................................................................... 31 loop filter amplifiers ............................................................... 32 connecting to a pwm controller (vctrl pin) ...................... 32 overvoltage and overcurrent comparators ........................... 32 step by step design example .................................................... 32 additional information ............................................................. 33 evaluation board ............................................................................ 34 introduction ................................................................................ 34 features and tes ts ....................................................................... 34 testing the AD8450 - e va l z ..................................................... 34 using the AD8450 ...................................................................... 36 schematic and artwork ............................................................. 37 outline dimensions ....................................................................... 41 ordering guide .......................................................................... 41 revision history 8 /15 rev. a to rev. b changes to table 2 ............................................................................ 8 added power supply sequencing section and power - on sequence section ............................................................................ 29 added power - off sequence .......................................................... 3 0 added additional information section ....................................... 33 changes to step 4: determine the control voltage for the cc loop, the shunt resistor, and the pgia gain section .............. 33 7 /14 rev. 0 to rev. a changes to general description ..................................................... 1 changes to pin 39 and pin 80 descriptions ................................ 1 0 changes to introduction section and figure 50 ........................ 22 changes to figure 52 ...................................................................... 24 changes to figure 5 5 ...................................................................... 26 changes to current shari ng bus and imax output section .. 27 changes to figure 58 ...................................................................... 28 changes to figure 59 ...................................................................... 30 changes to evaluat ion board section .......................................... 33 1 /1 4 revision 0: initial version
data sheet AD8450 rev. b | page 3 of 41 specifications avc c = + 25 v, avee = ? 5 v ; avc c = + 15 v, avee = ? 15 v ; dvcc = + 5 v ; pgia g ain = 26, 66, 133, or 200; pgda g ain = 0.2, 0.27, 0.4, or 0.8 ; t a = 25c, unless otherwise noted. table 1 . parameter test condition s /comments min typ max unit current sense pgia internal fixed gains 26, 66, 133, 200 v/v gain error v ismea = 10 v 0.1 % gain drift t a = t min to t max 3 ppm/c gain nonlinearity v ismea = 10 v , r l = 2 k? 3 ppm offset voltage (rti) gain = 200 , isrefh and isrefl pins grounded ?1 1 0 + 1 1 0 v offset voltage drift t a = t min to t max 0.6 v/c input bias current 15 30 na temperature coefficient t a = t min to t max 1 5 0 pa/c input offset current 2 na temperature coefficient t a = t min to t max 1 0 pa/c input common - mode voltage range v isvp ? v isvn = 0 v avee + 2.3 avcc ? 2.4 v over temperature t a = t min to t max avee + 2.6 avcc ? 2.6 v overvoltage input range av cc ? 5 5 av ee + 55 v differential input impedance 150 g? input common - mode impedance 150 g? output voltage swing avee + 1.5 avcc ? 1. 2 v over temperature t a = t min to t max avee + 1.7 avcc ? 1. 4 v capacitive load drive 1000 pf short - circuit current 40 ma reference input voltage range isrefh and isrefl pins tied together avee avcc v reference input bias current v is vp = v is vn = 0 v 5 a output voltage level shift isrefl pin grounded maximum isref h pin connected to vref pin 1 7 20 23 mv scale factor v ismea /v isrefh 6.8 8 9.2 mv/v cmrr v cm = 2 0 v gain = 26 108 db gain = 66 116 db gain = 133 122 db gain = 200 126 db temperature coefficient t a = t min to t max 0.01 v /v /c psrr v s = 20 v gain = 26 108 122 db gain = 66 116 130 db gain = 133 122 136 db gain = 200 126 140 db voltage noise f = 1 k hz gain = 26 9 nv/hz gain = 66 8 nv/hz gain = 133 7 nv/hz gain = 200 7 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz, all fixed gains 0.2 v p -p current noise f = 1 k hz 80 fa/hz current noise , peak -to - peak f = 0.1 hz to 10 hz 5 pa p -p
AD8450 data sheet rev. b | page 4 of 41 parameter test condition s /comments min typ max unit small signal ?3 db bandwidth gain = 26 1.5 mhz gain = 66 630 khz gain = 133 330 khz gain = 200 220 khz slew rate v ismea = 10 v 5 v/s voltage sense pgda internal fixed gains 0.2, 0.27, 0.4, 0.8 v/v gain error v in = 10 v 0.1 % gain drift t a = t min to t max 3 ppm/c gain nonlinearity v bvmea = 10 v, r l = 2 k? 3 ppm offset voltage (rto) bvrefh and bv refl pins grounded 500 v offset voltage drift t a = t min to t max 4 v/c differential input voltage range gain = 0.8, v bvn0 = 0 v, v bvrefl = 0 v avcc = +15 v, avee = ?15 v ?16 + 16 v avcc = +25 v, avee = ?5 v ? 4 + 29 v input common - mode voltage range gain = 0.8, v bvmea = 0 v avcc = +15 v, avee = ?15 v ?27 + 27 v avcc = +25 v, avee = ?5 v ?7 + 50 v differential input impedance gain = 0.2 800 k? gain = 0.27 600 k? gain = 0.4 400 k? gain = 0.8 200 k? input common - mode impedance gain = 0.2 240 k? gain = 0.27 190 k? gain = 0.4 140 k? gain = 0.8 90 k? output voltage swing avee + 1.5 avcc ? 1. 5 v over temperature t a = t min to t max avee + 1.7 avcc ? 1. 7 v capacitive load drive 1000 pf short - circuit current 30 ma reference input voltage range bv refh and bv refl pins tied together avee avcc v output voltage level shift b v refl pin grounded maximum bv refh pin connected to vref pin 4.5 5 5.5 mv scale factor v bvmea /v b v refh 1.8 2 2.2 mv/v cmrr v cm = 10 v, all fixed gains, rto 80 db temperature coefficient t a = t min to t max 0.05 v /v /c psrr v s = 20 v, all fixed gains, rto 100 db output voltage noise f = 1 khz , rti gain = 0.2 325 nv/hz gain = 0.27 250 nv/hz gain = 0.4 180 nv/hz gain = 0.8 105 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz , rti gain = 0.2 6 v p - p gain = 0.27 5 v p -p gain = 0.4 3 v p -p gain = 0.8 2 v p -p
data sheet AD8450 rev. b | page 5 of 41 parameter test condition s /comments min typ max unit small signal ?3 db bandwidth gain = 0.2 420 khz gain = 0.27 730 khz gain = 0.4 940 khz gain = 0.8 1000 khz slew rate 0.8 v/ s constant current and constant voltage loop filter amplifiers offset voltage 150 v offset voltage drift t a = t min to t max 0.6 v/c input bias current ?5 + 5 na over temperature t a = t min to t max ?5 + 5 na input common - mode voltage range avee + 1.5 avcc ? 1.8 v output voltage swing v vcln = avee + 1 v, v vclp = avcc ? 1 v avee + 1. 5 avcc ? 1 v over temperature t a = t min to t max avee + 1. 7 avcc ? 1 v closed - loop output impedance 0.01 ? capacitive load drive 1000 pf source short - circuit current 1 ma sink short - circuit current 40 ma open - loop gain 140 db cmrr v cm = 10 v 100 db psrr v s = 20 v 100 db voltage noise f = 1 khz 10 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz 0.3 v p -p current noise f = 1 k hz 80 f a/hz current noise , peak -to - peak f = 0.1 hz to 10 hz 5 p a p -p small signal gain bandwidth product 3 mhz slew rate v vint = 10 v 1 v/s cc to cv transition time 1.5 s uncommitted op amp offset voltage 150 v offset voltage drift t a = t min to t max 0.6 v/c input bias current ?5 + 5 na over temperature t a = t min to t max ?5 + 5 na input common - mode voltage range avee + 1.5 avcc ? 1.8 v output voltage swing avee + 1.5 avcc ? 1. 5 v over temperature t a = t min to t max avee + 1. 7 avcc ? 1.5 v closed - loop output impedance 0.01 ? capacitive load drive 1000 pf short - circuit current 40 ma open - loop gain r l = 2 k? 140 db cmrr v cm = 10 v 100 db psrr v s = 20 v 100 db voltage noise f = 1 khz 10 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz 0.3 v p -p current noise f = 1 khz 80 fa/hz current noise , peak -to - peak f = 0.1 hz to 10 hz 5 pa p -p small signal gain b andwidth product 3 mhz slew rate v oavo = 10 v 1 v/s
AD8450 data sheet rev. b | page 6 of 41 parameter test condition s /comments min typ max unit current sharing bus amplifier nominal gain 1 v/v offset voltage 150 v offset voltage drift t a = t min to t max 0.6 v/c output voltage swing avee + 1. 5 avcc ? 1. 5 v over temperature t a = t min to t max avee + 1. 7 avcc ? 1. 7 v capacitive load drive 1000 pf source short - circuit current 40 ma s ink short - circuit current 0 .5 ma cmrr v cm = 10 v 100 db psrr v s = 20 v 100 db voltage noise f = 1 khz 1 0 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz 0.4 v p -p small signal ?3 db bandwidth 3 mhz slew rate v c s = 10 v 1 v/s transition time 1.5 s current sharing, vint , and constant voltage buffers nominal gain 1 v/v offset voltage 150 v offset voltage drift t a = t min to t max 0.6 v/c input bias current cv buffer only ?5 + 5 na over temperature t a = t min to t max ?5 + 5 na input voltage range avee + 1.5 avcc ? 1.8 v output voltage swing current sharing and constant voltage buffers avee + 1. 5 avcc ? 1. 5 v over temperature t a = t min to t max avee + 1. 7 avcc ? 1.5 v vint buffer v vcln ? 0.6 v vclp + 0.6 v over temperature t a = t min to t max v vcln ? 0.6 v vclp + 0.6 v output clamps voltage range vint buffer only vclp pin v vcln avcc ? 1 v vcln pin avee + 1 v vcl p v closed - loop output impedance 1 ? capacitive load drive 1000 pf short - circuit current 40 ma psrr v s = 20 v 100 db voltage noise f = 1 khz 10 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz 0.3 v p -p current noise f = 1 khz, cv buffer only 8 0 fa/hz current noise , peak -to - peak f = 0.1 hz to 10 hz 5 pa p -p small signal ?3 db bandwidth 3 mhz slew rate v out = 1 0 v 1 v/s overcurrent and overvoltage fault comparators high threshold voltage with respect to ovpr and ocpr pins 30 45 mv temperature coefficient 100 v/c low threshold voltage with respect to ovpr and ocpr pins ?45 ? 30 mv temperature coefficient ?100 v/c input bias current 250 na input voltage range ovpr , ocpr, ovps, and ocp s pins avee avcc ? 3 v differential input voltage range ?7 + 7 v
data sheet AD8450 rev. b | page 7 of 41 parameter test condition s /comments min typ max unit fault output logic levels fau lt pin ( pin 46) output voltage high, v oh i load = 200 a 4.5 v output voltage low, v ol i load = 200 a 0.5 v propagation delay c load = 10 pf 500 n s fault rise time c load = 10 pf 150 ns fault fall time c load = 10 pf 150 ns voltage reference nominal output voltage with respect to agnd 2.5 v output voltage error 1 % temperature drift t a = t min to t max 10 ppm/c line regulation v s = 1 0 v 40 ppm/v load regulation i vref = 1 ma (source only) 400 ppm/ ma output current , sourcing 10 ma voltage noise f = 1 k hz 100 nv/hz voltage noise , peak -to - peak f = 0.1 hz to 10 hz 5 v p -p digital interface , mode input mode pin ( pin 39) input voltage high, v ih with respect to dgnd 2.0 dvcc v input voltage low, v il with respect to dgnd dgnd 0.8 v mode switching time 500 ns power supply operating voltage range avcc 5 3 6 v avee ? 31 0 v analog supply range avcc ? avee 5 36 v dvcc 3 5 v quiescent current avcc 7 10 ma avee 6.5 10 ma dvcc 40 70 a temperature range for specified performance ?40 +85 c operational ? 55 + 125 c
AD8450 data sheet rev. b | page 8 of 41 absolute maximum rat ings table 2 . parameter rating analog supply voltage (avcc ? avee) 36 v digital supply voltage ( dvcc ? dgnd ) 36 v maximum voltage at input pin s ( isvp, isvn, bvpx , and bvnx ) avee + 55 v minimum voltage at input pins ( isvp, isvn, bvpx , and bvnx ) av cc ? 55 v maximum voltage at all input pins , except isvp, isvn, bvpx , and bvnx avcc minimum voltage at all input pins , except isvp, isvn, bvpx , and bvnx avee maximum digital supply voltage with r espect to the positive analog supply (dvcc ? avcc) + 0.5 v minimum digital supply voltage with r espect to the nega tive analog supply (dvcc ? avee) ?0.5 v maximum digital ground with r espect to the positive analog supply (dgnd ? avcc) + 0.5 v minimum digital ground with r espect to the negative analog supply (dgnd ? avee) ?0.5 v maximum analog ground with r espect to the positive analog supply (agnd ? avcc) + 0.5 v minimum analog ground with r espect to the negative analog supply (agnd ? avee) ?0.5 v maximum analog ground with r espect to the digital ground (agnd ? dgnd ) + 0.5 v minimum analog ground with r espect to the digital ground (agnd ? dgnd) ?0.5 v operating temperature range ?40 c to + 8 5c s torage temperature range ? 65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operat ion of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance the ja value assume s a 4 - layer jedec st andard board with zero airflow. table 3 . thermal resistance package type ja unit 80- lead lqfp 54.7 c/w esd caution
data sheet AD8450 rev. b | page 9 of 41 pin configuration and fu nction descriptions notes 1. nc = no connect. 2 rgp 3 rgps 4 isgp0 7 isgp1s 6 isgp1 5 isgp0s 1 isvp 8 isgp2 9 isgp3 10 rfbp 12 isgn3 13 isgn2 14 isgn1s 15 isgn1 16 isgn0s 17 isgn0 18 rgns 19 rgn 20 isvn 11 rfbn 59 58 57 54 55 56 60 53 52 vctrl vcln avcc vve1 nc vint vclp vve0 nc 51 vvp0 49 vset 48 nc 47 dvcc 46 fault 45 dgnd 44 ocps 43 ocpr 42 vref 41 ovpr 50 vsetbf 21 bvp3s 22 bvp3 23 bvp2 24 bvp1 25 bvp0 26 vref 27 bvrefh 28 agnd 29 bvrefl 30 bvrefls 31 bvn0 32 bvn1 33 bvn2 34 bvn3 35 bvn3s 36 avee 37 bvmea 38 avcc 39 mode 40 ovps 80 csh 79 imax 78 oavp 77 isrefls 76 isrefl 75 agnd 74 isrefh 73 vref 72 avee 71 ismea 70 avcc 69 oavn 68 oavo 67 iset 66 nc 65 ive0 64 ive1 63 nc 62 vint 61 avee pin 1 AD8450 top view (not to scale) 1 1966-002 figure 2. pin configuration table 4 . pin function descriptions pin no. mnemonic in put / ou tpu t 1 description 1, 20 isvp, isvn i nput current sense instrumentation amplifier p ositive ( n oninverting) and n egative ( i nverting) i nput s . connect these pins across the current sense shunt resistor. 2, 19 rgp, rgn n/a current sense instrumentation amplifier g ain s etting p ins. connect these pins to the appropriate resistor network gain pins to select the current sense gain ( see table 5 ). 3, 18 rgps, rgns n/a kelvin sense pins for the current sense instrumentation amplifier g ain s etting p ins ( rgp and rgn ) . 4, 6 , 8, 9 , 12, 13 , 15, 17 isgp0, isgp1, isgp2, isgp3, isgn3, isgn2, isgn1, isgn0 n/a current s ense i nstrumentation a mplifier r esistor n etwork gain pins ( see table 5 ). 5, 7, 14, 16 isgp0s, isgp1s, isgn 1 s, isgn0s n/a kelvin s ense p ins for the isgp0 , isgp1 , isgn1 , and isgn0 pins . 10, 11 rfbp, rfbn o utput current s ense p reamplifier p ositive and n egative o utputs. 21, 35 bvp3s, bvn3s n/a kelvin s ense p ins for the v oltage s ense d ifference a mplifier i nputs bvp3 and bvn3. 22, 23, 24, 25, 31, 32, 33, 34 bvp3, bvp2, bvp1, bvp0, bvn0, bvn1, bvn2, bvn3 i nput v oltage s ense d ifference a mplifier i nputs . each input pair (bvpx and bvnx) corresponds to a different voltage sense gain (s ee table 6 ). 26, 42, 73 vref output voltage r eference o utput p ins. vref = 2.5 v. 2 7 b v refh i nput reference i nput for the voltage s ense d ifference a mplifier. t o level shift the voltage sense difference amplifier output by approximately 5 mv , c onnect this pin to the vref pin . otherwise, connect t his pin t o the bvr efl pin . 28, 75 agnd n/a analog g round p ins. 29 b v refl i nput reference i nput for the voltage s ense d ifference a mplifier . the d efault connection is to ground. 30 b v refls n/a kelvin s ense p in for the bvr efl p in.
AD8450 data sheet rev. b | page 10 of 41 pin no. mnemonic in put / ou tpu t 1 description 36, 61, 72 avee n/a analog n egative s upply p ins. the d efault voltage is ?5 v . 38, 57, 70 avcc n/a analog p ositive s upply p ins . the d efault voltage is +25 v . 37 bvmea output voltage s ense d ifference a mplifier o utput. 39 mode i nput ttl - compliant l ogic i nput to s elect the c harge or d ischarge m ode. l ow = discharge, high = charge. 40 ovps i nput noni nverting sen se i nput of the o vervoltage p rotection c omparator. 41 ovpr i nput i nverting reference i nput of the o vervoltage p rotection c omparator . typically , this pin connects to the 2.5 v reference voltage (vref) . 43 ocpr i nput i nverting reference i nput of the o vercurrent p rotection s ense c omparator . typically , this pin connects to the 2.5 v reference voltage (vref) . 44 ocps i nput noni nverting sen se i nput of the o vercurrent p rotection s ense c omparator. 45 dgnd n/a digital g round p in. 46 fau lt output overvoltage or o vercurrent f ault d etection l ogic o utput ( a ctive l ow). 47 dvcc n/a digital s upply. the d efault voltage is +5 v. 48, 52, 55, 63, 66 nc n/a no co nnect . there are no int ernal connections to these pins . 49 vset i nput target v oltage for the v oltage s ense c ontrol l oop. 50 vsetbf output buffered v oltage vset. 51 vvp0 i nput noni nverting i nput of the v oltage s ense i ntegrator for discharge m ode. 53 vve0 i nput inverting i nput of the v oltage s ense i ntegrator for discharge m ode . 54 vve1 i nput inverting i nput of the v oltage s ense i ntegrator for charge m ode . 56, 62 vint output minimum o utput of the v oltage s ense and c urrent s ense i ntegrator a mplifiers. 58 vcln i nput low c lamp v oltage for vctrl. 59 vctrl output controller o utput v oltage. connect this pin to the input of the pwm c ontroller ( for example, the comp pin of the adp1972 ). 60 vclp i nput high c lamp v oltage for vctrl. 64 ive1 i nput inverting i nput of the c urrent s ense i ntegrator for c harge m ode. 65 ive0 i nput inverting i nput of the c urrent s ense i ntegrator for dis charge m ode . 67 iset i nput target v oltage for the current s ense c ontrol l oop. 68 oavo output output of the u ncommitted o perational a mplifier . 69 oavn i nput inverting i nput of the u ncommitted o perational a mplifier . 71 ismea output current s ense i nstrumentation a mplifier o utput. 74 isrefh i nput reference i nput for the c urrent s ense a mplifier. t o l evel shift the current sense instrumentation amplifier output by approximately 20 mv , c onnect this pin to the vref pin . otherwise, connect this pin to the isrefl pin . 76 isrefl i nput reference i nput for the c urrent s ense a mplifier . the d efault connection is to ground. 77 isrefls n/a kelvin s ense p in for the isrefl p in. 78 oavp i nput non inverting i nput of the u ncommitted o perational a mplifier. 79 imax output maximum voltage of a ll v oltages a pplied to the c urrent s haring (csh) p in . 80 csh n/a current s haring b us . 1 n/a means not applicable.
data sheet AD8450 rev. b | page 11 of 41 typical performance characteristics t a = 25c, av cc = +25 v, avee = ? 5 v, r l = , unless otherwise not ed. pgia c haracteristics 30 ?10 ?5 0 5 10 15 20 25 ?10 ?5 0 5 10 15 20 25 30 input common-mode voltage (v) output voltage (v) valid for all gains avcc = +25v avee = ?5v 1 1966-003 figure 3. input common - mode voltage vs. output voltage for avcc = +25 v and avee = ?5 v 15 ?15 ?10 ?5 0 5 10 ?35 ?30 ?10 ?20 0 45 30 40 20 10 ?25 ?5 ?15 5 35 25 15 input current (ma) input voltage (v) avcc = +25v avee = ?5v gain = 200 gain = 26 1 1966-005 figure 4. input overvoltage performance for avcc = +25 v and avee = 5 v 17.0 16.8 16.6 16.4 16.2 16.0 15.8 15.6 15.4 15.2 15.0 ?15 ?10 ?5 0 5 10 15 20 25 input bias current (na) input common-mode voltage (v) valid for all gains avcc = +15v avee = ?15v avcc = +25v avee = ?5v 1 1966-007 figure 5. input bias current vs. input common - mode voltage 20 ?20 ?15 ?10 ?5 0 5 10 15 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode voltage (v) output voltage (v) valid for all gains avcc = +15v avee = ?15v 1 1966-004 figure 6. input c ommon - mode voltage vs . output voltage for avcc = +15 v and avee = 15 v 15 ?15 ?10 ?5 0 5 10 ?45 ?35 ?40 ?30 ?10 ?20 0 45 30 40 20 10 ?25 ?5 ?15 5 35 25 15 input current (ma) input voltage (v) avcc = +15v avee = ?15v gain = 200 gain = 26 1 1966-006 figure 7. input overvoltage performance for avcc = + 15 v and avee = 15 v 20 19 18 17 16 15 14 13 12 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 input bias current (na) temperature (c) ?i b +i b 1 1966-008 figure 8. input bias current vs. temperature
AD8450 data sheet rev. b | page 12 of 41 20 ?100 ?80 ?60 ?40 ?20 0 ?40?30?20?100 102030405060708090 gain error (v/v) temperature (c) gain = 200 gain = 66 gain = 133 gain = 26 11966-009 figure 9. gain error vs. temperature 0.3 ?0.3 ?0.2 ?0.1 0 0.1 0.2 ?40?30?20?100 102030405060708090 cmrr (v/v) temperature (c) gain = 200 gain = 133 gain = 66 gain = 26 avcc = +25v avee = ?5v 11966-010 figure 10. normalized cmrr vs. temperature 50 40 ?20 ?10 0 10 20 30 100 10m 1m 100k 10k 1k gain (db) frequency (hz) avcc = +15v avee = ?15v gain = 200 gain = 133 gain = 66 gain = 26 11966-011 figure 11. gain vs. frequency 160 50 60 70 80 90 100 110 120 130 140 150 0.1 1 10 100 100k 10k 1k cmrr (db) frequency (hz) gain = 200 gain = 133 gain = 66 gain = 26 11966-012 figure 12. cmrr vs. frequency 160 0 60 40 20 80 100 120 140 1 10 100 1m 100k 10k 1k psrr (db) frequency (hz) 200 133 66 26 gain avcc avee 11966-013 figure 13. psrr vs. frequency 100 1 10 0.1 1 10 100 100k 10k 1k spectral density voltage noise (nv/ 11966-014 figure 14. spectral density voltage noise, rti vs. frequency
data sheet AD8450 rev. b | page 13 of 41 pgda characteristics 60 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?10 ?5 0 5 10 15 20 25 30 input common-mode voltage (v) output voltage (v) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 11966-015 figure 15. input common-mode voltage vs. output voltage for avcc = +25 v and avee = ?5 v 0 ?50 ?40 ?30 ?20 ?10 100 1k 10k 100k 1m gain (db) frequency (hz) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 valid for all rated supply voltages 11966-019 figure 16. gain vs. frequency 0 ?120 ?100 ?80 ?60 ?40 ?20 100 1k 10k 100k 1m cmrr (db) frequency (hz) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 valid for all rated supply voltages 11966-020 figure 17. cmrr vs. frequency 50 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode voltage (v) output voltage (v) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 11966-016 figure 18. input common-mode voltage vs. output voltage for avcc = +15 v and avee = ?15 v 50 ?200 ?150 ?100 ?50 0 ?40?30?20?100 102030405060708090 gain error (ppm) temperature (c) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 11966-017 figure 19. gain error vs. temperature 3 ?3 ?2 ?1 0 1 2 ?40?30?20?100 102030405060708090 cmrr (v/v) temperature (c) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 11966-018 figure 20. normalized cmrr vs. temperature
AD8450 data sheet rev. b | page 14 of 41 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10 100 100k 10k 1k frequency (hz) psrr (db) 0.80 0.40 0.27 0.20 gain avcc avee valid for all rated supply voltages 1 1966-021 figure 21 . psrr vs. frequency 1k 10 100 0.1 1 10 100 100k 10k 1k spectral density voltage noise (nv/hz) frequency (hz) gain = 0.80 gain = 0.40 gain = 0.27 gain = 0.20 rti 1 1966-022 figure 22 . spectral density voltage noise , rti vs. frequency
data sheet AD8450 rev. b | page 15 of 41 cc and cv loop filter amplifiers, uncommitted op amp, and vset buffer 500 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 ?15 ?10 ?5 0 5 10 15 20 25 input offset voltage (v) input common-mode voltage (v) avcc = +25v avee = ?5v avcc = +15v avee = ?15v 11966-023 figure 23. input offset voltage vs. input common-mode voltage for two supply voltage combinations 100 0 10 20 30 40 50 60 70 80 90 ?15 ?10 ?5 0 5 10 15 20 25 input bias current (pa) input common-mode voltage (v) avcc = +25v avee = ?5v avcc = +15v avee = ?15v 11966-024 figure 24. input bias current vs. input common-mode voltage for two supply voltage combinations 100 ?40 ?20 0 20 40 60 80 ?40?30?20?100 102030405060708090 input bias current (na) temperature (c) ?i b +i b 11966-025 figure 25. input bias current vs. temperature 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40?30?20?100 102030405060708090 output source current (ma) temperature (c) constant current loop and constant voltage loop amplifiers avcc = +25v avee = ?5v avcc = +15v avee = ?15v 11966-026 figure 26. output source current vs. temperature for two supply voltage combinations 120 ?40 ?20 0 20 40 60 80 100 ? 45.0 ?225.0 ?202.5 ?180.0 ?157.5 ?135.0 ?112.5 ?90.0 ?67.5 10 100 1k 10k 100k 1m 10m open-loop gain (db) phase (degrees) frequency (hz) phase gain 11966-027 figure 27. open-loop gain and phase vs. frequency 160 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) uncommitted op amp constant current loop and constant voltage loop filter amplifiers 11966-028 figure 28. cmrr vs. frequency
AD8450 data sheet rev. b | page 16 of 41 140 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m psrr (db) frequency (hz) +psrr ?psrr 1 1966-029 figure 29 . psrr vs. frequency 1k 1 10 100 0.1 1 10 100 100k 10k 1k spectral density voltage noise (nv/hz) frequency (hz) 1 1966-030 figure 30 . range of spectral density voltage noise vs. frequency for the op a mps and buffers 1.5 ?1.5 ?0.5 0.5 1.0 ?1.0 0 ?15 35 30 25 20 15 10 5 0 ?5 ?10 output voltage (v) time (s) transition avcc = +15v avee = ?15v iset vctrl 1 1966-031 figure 31 . cc to cv transition
data sheet AD8450 rev. b | page 17 of 41 vint buffer 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 output voltage swing (v) temperature (c) vctrl output wrt vclp vctrl output wrt vcln vclp and vcln reference valid for all rated supply voltages 1 1966-032 figure 32 . output voltage swing with r espect to vclp and vcln vs. temperature 15 ?15 ?10 ?5 0 5 10 100 1m 100k 10k 1k load resistance () output voltage swing (v) ?40c +25c +85c temp vclp vcln 1 1966-033 figure 33 . output voltage swing vs. load resistance at three temperatures 6 ?1 0 1 2 3 4 5 10 40 35 30 25 20 15 output current (ma) clamped output voltage (v) vclp vcln v in = +6v/?1v temp vclp 0c ?40c +25c +85c vcln 1 1966-034 figure 34 . clamped output voltage vs. output current at four temperatures 6 ?1 0 1 2 3 4 5 0 40 35 30 25 20 15 10 5 time (s) output voltage (v) c l = 100pf r l = 2k 1 1966-035 figure 35 . large signal transient response, r l = 2 k, c l = 100 pf 0.20 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 10 9 8 7 6 5 4 3 2 1 time (s) output voltage (v) c l = 10pf c l = 100pf c l = 510pf c l = 680pf c l = 1000pf 1 1966-036 figure 36 . small signal transient response vs. capacitive load 100 10 1 0.1 10 100 1k 10k 100k 1m output impedance () frequency (hz) 1 1966-037 figure 37 . output impedance vs. frequency
AD8450 data sheet rev. b | page 18 of 41 current sharing amplifier ? 0.20 ?0.50 ?0.45 ?0.40 ?0.35 ?0.30 ?0.25 ?40?30?20?100 102030405060708090 output sink current (ma) temperature (c) valid for all rated supply voltages 11966-038 figure 38. output sink current vs. temperature 3 ?3 ?2 ?1 0 1 2 ?15?10?5 0 5 101520253035 output voltage (v) time (s) avcc = +15v avee = ?15v ismea imax transition 11966-039 figure 39. current sharing bus transition characteristics
data sheet AD8450 rev. b | page 19 of 41 comparators 500 300 350 400 450 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 propagation delay (ns) temperature (c) low to high transition high to low transition 1 1966-040 figure 40 . propagation delay vs. temperature 1600 1400 1200 1000 800 600 400 200 0 100 200 300 400 500 600 700 800 900 1000 propagation delay (ns) load capacitance (pf) low to high transition high to low transition 1 1966-041 figure 41 . propagation delay vs. load capacitance 1000 900 800 700 600 500 400 300 200 100 0 10 100 1k 10k propagation delay (ns) source resistance () low to high transition high to low transition 1 1966-042 figure 42 . propagation delay vs. source resistance 5 4 3 2 1 0 0 200 400 100 300 500 output voltage (v) output current (a) ?40c +25c +85c temp i source i sink valid for all rated supply voltages 1 1966-043 figure 43 . output voltage vs. output current at three temperatures 6 5 4 3 2 1 0 ?1 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 hysteresis (v) input voltage (v) t a = ?40c t a = +25c t a = +85c 1 1966-044 figure 44 . comparator transfer function at three temperatures
AD8450 data sheet rev. b | page 20 of 41 reference characteristics 2.51 2.50 2.49 2.48 2.47 2.46 0 1 2 3 4 5 6 7 8 9 10 output voltage (v) output current?sourcing (ma) t a = ?40c t a = +25c t a = ?20c t a = +85c t a = 0c 1 1966-045 avcc = +25v avee = ?5v figure 45 . output voltage vs. output current (sourcing) o ver temperature 2.9 2.8 2.7 2.6 2.5 2.4 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 output voltage (v) output current?sinking (ma) t a = +85c t a = +25c t a = 0c t a = ?20c t a = ?40c 1 1966-046 avcc = +25v avee = ?5v figure 46 . output voltage vs. output current (sinking) o ver temperature 1200 1100 1000 900 800 700 600 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 load regulation (ppm/ma) temperature (c) avcc = +25v avee = ?5v 1 1966-047 figure 47 . source and sink load regulation vs. temperature 1k 10 100 0.1 1 10 100 100k 10k 1k spectral density voltage noise (nv/hz) frequency (hz) 1 1966-048 figure 48 . spectral density voltage noise vs. frequency
data sheet AD8450 rev. b | page 21 of 41 theory o f operation introduction t o form and test a battery, the battery must undergo charge and discharge cycles. during these cycles, the battery terminal current and voltage must be precisely controlled to prevent battery failure or a reduction in the capacity of the battery . therefore, battery formation and test systems require a high precision analog front end to monitor the battery current and terminal voltage. the analog front end of the AD8450 includes a precision current sense programmable gain instrumentation amplifier ( pgia ) to measure the battery current , and a precision voltage sense program mable gain difference amplifier ( pgda ) to measure the battery voltage. the gain programmability of the pgia allows the system to set the battery charg e /discharg e current to any of four discrete values with the same shunt resistor . the gain program - mability of the pgda allows the system to handle up to four batteries in series (4s) . 17 18 15 16 8 7 6 5 4 3 2 14 13 9 12 11 10 isvp rgp rgps isgp1 isgp0s isgp0 isgp2 isgp3 rfbp isgn3 isgn2 isgn1 isgn0 isgn0s rgns rgn isvn rfbn 19 34 35 27 25 24 23 22 21 33 32 31 30 29 59 54 56 60 53 51 49 44 43 41 50 ? + 58 46 39 ? + ? + ? + ? + ? + ? + ? + avcc avee avee 1 1 1 20 42 37 40 26 28 36 38 57 55 52 47 48 45 csh isrefh imax vref isrefls isrefl oavp ive1 ismea ive0 iset vint oavo oavn nc agnd avee avcc nc avee vctrl vcln vve1 vint vclp vve0 vvp0 vset fault ocps ocpr ovpr vsetbf vref avcc nc nc dvcc nc dgnd 64 62 69 65 68 67 73 71 78 74 77 76 80 79 61 63 70 72 75 66 bvrefh bvp3 bvp3s bvrefl bvp1 bvp0 bvp2 bvn3s bvrefls bvn3 bvn2 ovps bvmea bvn1 bvn0 mode vref agnd avee avcc vint buffer vset buffer cs bus amplifier uncommitted op amp overcurrent fault comparator overvoltage fault comparator cs buffer 10k 10k 10k 10k 10k 10k 10k 10k 202 305 625 1667 10k 10k 20k 19.2k 100k 100k 100k 100k 100 100k 100k 100k 80k 79.9k isgn1s +/? +/? isgp1s ? + 50k 100k 806 100k cv loop filter amplifier cc loop filter amplifier battery current sensing pgia battery voltage sensing pgda constant current and voltage loop filter amplifiers 1 avee avcc ? + AD8450 mode 1 = charge 0 = discharge 1.1ma 2.5v vref agnd 0.2ma 0.2ma 11966-049 nor figure 49 . AD8450 detailed block diagram
AD8450 data sheet rev. b | page 22 of 41 battery formation and test systems charge and discharge batteries using a constant current / constant voltage (cc / cv) algorithm. in other words, the system first force s a set constant current in or out of the battery until the battery voltage reaches a target value. at this point, a set constant voltage is forced across the battery terminals. the AD8450 provides two control loops a constant current ( cc ) loop and a constant voltage ( cv) loop that transition automatically after the battery reaches the user defined target voltage. these loops are implemented via two precision specialty amplifiers with external feedb ack networks that set the transfer function of the cc and cv loops. moreover, in the AD8450 , these loops reconfigure themselves to charge or discharge the battery by toggling the mode pin . b attery formation and test systems must also be able to detect overvoltage and overcurrent conditions in the battery to prevent damag e to the battery and/or the control system. the AD8450 includes two comparators to detect overcurrent and overvoltage events. these comparators output a logic low at the fault pin when either comparator is tripped. battery formation and test systems used to condition high current battery cells often employ multiple ind ependent channels to charge or discharge high currents to or from the battery. to maximize efficiency, these systems benefit from circuitry that enables precise current sharing (or balancing) among the channels that is, circuitry that actively matches the output current of each channel. the AD8450 includes a specialty precision amplifier that detects the maximum output current among several channels by identifying the channel with the maximum volt age at its pgia output. this maximum voltage can then be compared to all the pgia output voltages to actively adjust the output current of each channel. figure 49 is a block diagram of the AD8450 that illustrates the distinct sections of the AD8450 , including the pgia and pgda measurement blocks, the loop filter amplifiers, the fault com - par a tors, and the current sharing circuitry. figure 50 is a block diagram of a battery formation and test system. battery level shifter adp1972 pwm vctrl sense resistor isvp isvn bvpx bvnx avcc output drivers battery current avee cv buffer ? + ? + 1 vint buffer vsetbf vset iset c d c d c d vint ismea bvmea vve1 vve0 vvp0 ive1 ive0 ? + ? + ocps ocpr ovpr vref overcurrent comparator overvoltage comparator fault ovps output filter pgda ? + ? + pgia system power conversion system loop compensation 1 set battery current v iset v vset set battery voltage power converter (switched or linear) AD8450 controller constant voltage loop filter amplifier constant current loop filter amplifier mode switches (3) c = charge d = discharge 11966-050 nor figure 50 . signal path of a li - ion battery f ormation and test system using the AD8450
data sheet AD8450 rev. b | page 23 of 41 programmable gain instrumentation amplifier (pgia) figure 51 is a block diagram of the pgia, which is used to monitor the battery current. the architecture of the pgia is the classic 3-op-amp topology, similar to the analog devices industry- standard ad8221 and ad620 . this architecture provides the highest achievable cmrr at a given gain, enabling high-side battery current sensing without the introduction of significant errors in the measurement. for more information about instru- mentation amplifiers, see a designer's guide to instrumentation amplifiers . 11966-051 10k? 20k ? 10k? 806 ? pgia +/? +/? rgp isgp0, isgp1, isgp2, isgp3 isgn0, isgn1, isgn2, isgn3 rgn isvn isvp connect for desired gain + current shunt ? current shunt ismea g = 2 subtractor 100k ? 19.2k ? isrefh isrefl vref polarity inverter polarity inverter mode rfbp ? + rfbn ? + gain networks (4) figure 51. pgia simplified block diagram gain selection the pgia includes four fixed internal gain options. the pgia can also use an external gain network for arbitrary gain selection. the internal gain options are established via four independent three-resistor networks, which are laser trimmed to a matching level better than 0.1%. the internal gains are optimized to minimize both pgia gain error and gain error drift, allowing the controller to set a stable charge/discharge current over temperature. if the built in internal gains are not adequate, the pgia gain can be set via an external three-resistor network. the internal gains of the pgia are selected by tying the inverting inputs of the pgia preamplifiers (rgp and rgn pins) to the corresponding gain pins of the internal three-resistor network (isgp[0:3] and isgn[0:3] pins). for example, to set the pgia gain to 26, tie the rgp pin to the isgp0 pin, and tie the rgn pin to the isgn0 pin. see table 5 for information about the gain selection connections. the external pgia gain is set by tying 10 k feedback resistors between the inverting inputs of the pgia preamplifiers (rgp and rgn pins) and the outputs of the pgia preamplifiers (rfbp and rfbn pins) and by tying a gain resistor (r g ) between the rgp and rgn pins. when using external resistors, the pgia gain is gain = 2 (1 + 20 k/ r g ) note that the pgia subtractor has a closed-loop gain of 2 to increase the common-mode range of the preamplifiers. reversing polarity when charging and discharging figure 50 shows that during the charge cycle, the power converter feeds current into the battery, generating a positive voltage across the current sense resistor. during the discharge cycle, the power converter draws current from the battery, generating a negative voltage across the sense resistor. in other words, the battery current polarity reverses when the battery discharges. in the constant current (cc) control loop, this change in polarity can be problematic if the polarity of the target current is not reversed. to solve this problem, the AD8450 pgia includes a multiplexer preceding its inputs that inverts the polarity of the pgia gain. this multiplexer is controlled via the mode pin. when the mode pin is logic high (charge mode), the pgia gain is noninverting, and when the mode pin is logic low (discharge mode), the pgia gain is inverting. pgia offset option as shown in figure 51, the pgia reference node is connected to the isrefl and isrefh pins via an internal resistor divider. this resistor divider can be used to introduce a temperature insensitive offset to the output of the pgia such that the pgia output always reads a voltage higher than zero for a zero differ- ential input. because the output voltage of the pgia is always positive, a unipolar adc can digitize it. when the isrefh pin is tied to the vref pin with the isrefl pin grounded, the voltage at the ismea pin is increased by 20 mv, guaranteeing that the output of the pgia is always positive for zero differential inputs. other voltage shifts can be realized by tying the isrefh pin to an external voltage source. the gain from the isrefh pin to the ismea pin is 8 mv/v. for zero offset, tie the isrefl and isrefh pins to ground. battery reversal and overvoltage protection the AD8450 pgia can be configured for high-side or low-side current sensing. if the pgia is configured for high-side current sensing (see figure 50) and the battery is connected backward, the pgia inputs may be held at a voltage that is below the negative power rail (avee), depending on the battery voltage. to prevent damage to the pgia under these conditions, the pgia inputs include overvoltage protection circuitry that allows them to be held at voltages of up 55 v from the opposite power rail. in other words, the safe voltage span for the pgia inputs extends from avcc ? 55 v to avee + 55 v.
AD8450 data sheet rev. b | page 24 of 41 programmable gain differen ce amplifier ( pgda ) figure 52 is a block diagram of the pgda , which is used to monitor the battery voltage. the architecture of the pgda is a subtractor amplifier with four selectable inputs : the bvp [ 0 :3 ] and bvn [ 0 :3 ] pin s. each input pair corresponds to one of the internal gains of the pgda: 0.2, 0.27, 0.4, and 0.8. these gain values allow the pgda to funnel the voltage of up to four 5 v batteries in series ( 4s ) to a level that can be read by a 5 v adc. see table 6 for information about the gain selection connection s . 11966-152 bvp3 bvrefl bvp1 bvp0 bvp2 bvn3 bvn2 bvn1 bvn0 100k 100k 100k 100k 80k 100k 100k 100k 100k 100 50k 79.9k pgda ? + bvrefh vref bvmea figure 52 . pgda simplified block diagram the resistors that form the pgda gain network are laser trimmed to a matching level better than 0.1%. this level of matching minimizes the gain error and gain error drift of the pgda while maximizing the cmrr of the pgda . this match - ing also allows the controller to set a stable target v oltage for the battery over temperature while rejecting the ground bounce in the battery negative terminal. like the pgia, the pgda can also level shift its output voltage via an internal resistor divider that is tied to the pg d a refer - ence node. this resi stor divider is connected to the bvrefh and bvrefl pins . when the bvrefh pin is tied to the vref pin with the bvrefl pin grounded , the voltage at the bvmea pin is increased by 5 m v, guaranteeing that the output of the pgda is always positive for zero differential inputs. other voltage shifts can be realized by tying the bvrefh pin to an external voltage source. the gain from the bvrefh pin to the bvmea pin is 2 m v / v. for zero offset, tie the bvrefl and bvrefh pins to ground. c c and cv loop filter amplifiers the constant current (cc) and constant voltage (cv) loop filter amplifiers are high precision, low noise specialty amplifiers with very low offset voltage and very low input bias current. thes e amplifiers serve two purposes: ? using external components, the amplifiers implement active loop filters that set the dynamics (transfer function) of the cc and cv loops. ? the amplifiers perform a seamless transition from cc to cv mode after the battery reaches its target voltage . figure 53 is the functional block diagram of the AD8450 cc and cv feedback loops for charge mode (mode pin is logic high). for illustration purposes, the external networks connected to the loop amplifiers are simple rc networks configured to form single - pole inverting integrators. the outputs of the cc and cv loop filter amplifiers are coupled t o the vint pin via an analog nor circuit (minimum output selector circuit) , such that they can only pull the vint node down. in other words, the loop amplifier that requires the lowest voltage at the vint pin is in control of the node. thus, only one loop amplifier, cc or cv, can be in control of the system charging control loop at a ny given time. iset ? + ? + cc loop amplifier cv loop amplifier ive1 vve1 analog nor isvn bvpx bvnx g da ? + ? + g ia ismea bvmea i bat pgia pgda v vset r2 c2 vset r1 c1 1 vctrl vcln vclp vint buffer v iset vbat sense resistor mode 5v ? + vint r s p o w e r converter vint iout isvp vctrl i power bus minimum output selector v4 v3 v3 < vctrl < v4 1 1966-053 figure 53 . functional block diagram of the cc and cv loops in charge mode (mode pin high)
data sheet AD8450 rev. b | page 25 of 41 the unity - gain amplifier ( vint b uffer ) buffers the vint pin and drives the vctrl pin . the vctrl pin is the control output of the AD8450 and the control input of the power converter. the v iset and v vset v oltage sources set the target constant current and the target constant voltage , respectively. when the cc and cv feedback loops are in steady state, the charging current is set at i bat_ss = s ia iset r g v g ia is the pgia gain. r s is the value of the shunt resistor. t he target voltage is set at v bat_ss = da vset g v here g da is the pgda gain. because the offset voltage of the loop amplifiers is in series with the target voltage sources , v iset and v vset , the high precision of these amplifiers minimizes this source of error. figure 54 shows a typical cc/cv charging profile for a li - ion battery . in the first stage of the charging process, the battery is charged with a constant current (cc) of 1 a. when the battery voltage r eaches a target voltage of 4.2 v, the charging process transitions such that the battery is charged with a constant voltage (cv) of 4.2 v. 1.25 0 0.25 0.50 0.75 1.00 5 0 1 2 3 4 0 5 4 3 2 1 current (a) voltage (v) time (hours) cc charge begins transition from cc to cv cc charge ends 1 1966-054 figure 54 . representative constant current to constant voltage transition near the e nd of a battery charging cy cle the following steps describe how the AD8450 implements the cc/ cv charg ing profile (see figure 53). in this scenario, th e battery begins in the fully discharged state , and th e system has just been turned on such that i bat = 0 a at time 0. 1. because t he voltages at the ismea and bvmea pins are below t he t arget voltages ( v iset and v vset ) at time 0 , both integrators begin to ramp, increasing the voltage at the vint node . 2. as the voltage at the vint node increases, the voltage at the vcrtl node rises, and the output current of the power converter, i bat , increa ses (assum ing that an increasing voltage at the vcrtl node increases the output current of the power converter). 3. when the i bat current reaches the cc steady state value, i bat_ss , the battery voltage is still below the target steady state value , v bat_ss . t herefore, the cv loop tries to keep pulling the vint node up while the cc loop tries to keep it at its current voltage . a t this point , the voltage at the ismea pin equals v iset , so the cc loop stops integrating. 4. because the loop amplifiers can only pull the vint node down due to the analog nor circuit, the cc loop takes control of the charging feedback loop and the cv loop i s disabled. 5. as the charging process continues, the battery voltage increases until it reaches the steady state value , v bat_ss , and t he voltage at the bvmea pin reaches the target voltage , v vset . 6. t he cv loop tries to pull the vint node down to reduce the charging current ( i bat ) and prevent the ba ttery voltage from rising any fa rther. at the same time, the cc loop tries to keep the vint node at its current voltage to keep the battery current at i bat_ss . 7. because the loop amplifiers can only pull the vint node down due to the analog nor circuit, the cv loop takes control of the charging feedback loop and the cc loop is disabled. the analog nor (minimum output selector ) circuit that coup les the outputs of the loop amplifiers is optimized to minimize the transition time from cc to cv control . any delay in the trans - ition cause s the cc loop to remain in control of the charge feedback loop after the battery voltage reache s its target value. therefore, the battery voltage continue s to rise beyond v bat_ss until the control loop transitions ; that is, the battery voltage overshoot s its target voltage. when the cv loop takes control of the charge fee dback loop, it reduces the battery voltage to the target voltage. a large overshoot in the battery voltage due to transition delays can damage the battery; thus, it is crucial to minimize delays by implementi ng a fast cc to cv transition.
AD8450 data sheet rev. b | page 26 of 41 iset ? + ? + cc loop amplifier cv loop amplifier ive0 vve0 analog nor isvn bvpx bvnx g da ? + ? + g ia ismea bvmea i bat pgia pgda v vset r2 c2 r2 c2 vset vsetbf vvp0 r1 c1 1 vctrl vcln vclp vint buffer v iset vbat sense resistor mode 0v ? + vint r s power converter vint iout isvp vctrl i power bus minimum output selector v4 v3 v3 < vctrl < v4 1 vset buffer 11966-055 figure 55 . functional block diagram of the cc and cv loops in discharge mode (mode pin low) figure 55 is the functional block diagram of the AD8450 cc and cv feedback loo ps for discharge mode (mode pin is logic low. in discharge mode , the feedback loops operate in a similar manner as in charge mode. the only difference is in the cv loop amplifier, which operates as a noninverting integrator in discharge mode. for illustration purposes, the external networks connected to the loop ampli fiers are simple rc networks configured to form single - pole integrators (see figure 55). compensation in battery formation and test systems, the cc and cv feedback loops have significantly different open - loop gain and crossover frequenc ies ; therefore, each loop requires its own frequency compensation. the active filter architecture of the ad8 450 cc and cv loops allows the frequency response of each loop to be set independently via external components. moreover, due to the internal switches in the cc and cv amplifiers, the frequency response of the loops in charge mode does not affect the frequ ency response of the loops in discharge mode. unlike simpler controllers that use passive networks to ground for frequency compensation, the AD8450 allows the use of feed - back networks for its cc and cv loop filter amplifiers. these networks enable the implementation of b oth pd (type ii) and pid (type iii) compensators. note that in charge mode, both the cc and cv loops implement inverting compensators, whereas in discharge mode, the cc loop implem ents an inverting compen - sator and the cv loop implements a non i nverting compensator. as a result, the cv loop in discharge mode includes an additional amplifier, vset buffer, to buffer the vs et node from the feed - back network (see fi gure 55). vint b uffer the unity - gain amplifier ( vint buffer ) is a clamp amplifier that drives the vctrl pin . the vctrl pin is the control output of the AD8450 and the control input of the power converter (see figure 53 and figure 55). the output voltage range of this amplifier is bounded by the clamp voltages at the vclp and vcln pins such that v vcl n ? 0. 5 v < v vctrl < v vclp + 0. 5 v th e reduction in the output voltage range of the amplifier is a safety feature that allows the AD8450 to drive devices such as the adp1972 pulse - width modulation ( pwm ) controller , whose input voltage range must not exceed 5.5 v (that is, the voltage at the comp pin of the adp1972 must be below 5.5 v) . m ode pin , charge and discharge control the mode pin is a ttl logic input that configures the AD8450 for either charge or discharge mode. a logic low ( v mode < 0.8 v ) corresponds to discharge mode, and a logic high ( v mode > 2 v ) corresponds to charge mode. internal to the AD8450 , the mode pin toggles all spdt switches i n the cc and cv loop amplifiers and invert s the gain polarity of the pgia.
data sheet AD8450 rev. b | page 27 of 41 over c urrent and over v oltage c omparators the AD8450 includes overcurrent protection (ocp) and over - voltage protection (ovp) comparators to detect overvoltage and overcurrent conditions in the battery. because the outputs of the comparators are combined by a nor logic gate , t hese comparators output a logic low at the fault pin when either comparator is tripped (see figure 49). the ocp and ovp comparators can be configured to detect a fault in one of two ways. in the configuration shown in figure 56, the voltages at the ismea and bvmea pins are divided down and compared to the internal 2.5 v reference of the AD8450 . in this configuration, the f ault pin register s a logic low (a fault condition) when v ismea > r2 r2 r1 + v bv mea > r3 r4 r3 + ? + ? + ocps ocpr ovpr vref fault ovps bvpx bvnx ismea bvmea isvp isvn ? + pgia ? + pgda nor r1 r3 r4 r2 11966-056 figure 56 . ovp and ocp comparator configuration using the internal reference alternatively, the outputs of the pgia and pgda can be tied directly to the sense inputs of the comparators ( ocps and ovps pins ) such that the voltages at the ismea and bvmea pins are compared to the external reference voltage s, v ocp_ref and v ovp_ref (see figure 57). in this configuration, the f ault pin register s a logic low (a fault condition) when v ismea > v ocp_ref or v bv mea > v ovp_ref ? + ? + ocps ocpr ovpr fault ovps bvpx bvnx ismea bvmea isvp isvn ? + pgia ? + pgda nor ? + ? + v ovp_ref v ocp_ref 1 1966-057 figure 57 . ovp and ocp comparator configuration using an external reference (for example, a dac)
AD8450 data sheet rev. b | page 28 of 41 current sharing bus and imax output battery formation and test systems that use multiple channels bridged together to condition high current battery cells require circuitry to balance the total output current among the channels. current balance, or current sharing (cs), can be implemented by actively match ing the output current of each channel during the battery charge/discharge process. the c urrent s haring b us amplifier is a precision unity - gain specialty amplifier with an output stage that can only pull up its output node (the cs h pin) . the amplifier is configured as a unity - gain buffer with its input connect ed to the ismea pin (the output of the pgia ) . if the cs h pin is left unconnected, the voltage at the pin is a replica of the voltage at the ismea pin . figure 58 is a functional block diagram of the current sharing circuit. in this example, channel 0 through channel n are bridged together to charge a high current battery. the cs output of each channel is tied to a common bus ( cs b us ) , which is buffered by the cs b uffer amplifier to the imax pin . by means of external resistors, the uncommitted operational amplifier is configured as a difference amplifier to measure the volta ge difference between the imax and ismea nodes . during the charge process, the charging current and, therefore, the voltage at the ismea pin, is slightly different in each channel due to m ismatches in the components that make up each channel. bec ause the cs bus amplifiers are driven by their respective pgias and have output stages that can only pull up their output nodes, the amplifier that requires the highest voltage takes control of the cs bus . therefore, the voltage at the cs bus is pulled up to match the v ismea voltage of the channel with the largest output current. the output voltage of the uncommitted op amp in each channel is proportional to the difference between the channels output current and the largest output current. this output voltage can t hen be used to form a feedback loop that actively corrects the channels output current by adjusting the channels target current and target voltage, that is, adjusting v iset and v vset v oltages . 1 1966-158 i_n channel n channel 1 imax isvp isvn ? + ismea pgia cs oavo oavn r s0 oavp r cs buffer cs bus amplifier ? + 1 ? + r r r channel 0 avee uncommitted op amp correction signal v cs ? v ismea channel 0 i_0 i_1 cs bus ibat i_0 figure 58 . functional block diagram of the current sharing circuit
data sheet AD8450 rev. b | page 29 of 41 applications information this section describes how to use the AD8450 in the context of a battery formation and test system. this section includes a design example of a small scale model of an actual system. an evaluation board for the AD8450 is available and is described in the evaluation board section. functional description the AD8450 is a precision analog front end and controller for battery formation and test systems. these systems use precision controllers and power stages to put batteries through charge and discharge cycles. figure 59 shows the signal path of a simplified switching battery formation and test system using the AD8450 controller and the adp1972 pwm controller. for more information about the adp1972 , see the adp1972 data sheet. the AD8450 is suitable for systems that form and test nicad, nimh, and li-ion batteries and is designed to operate in conjunction with both linear and switching power stages. the AD8450 includes the following blocks (see figure 49 and the theory of operation section for more information). ? pin programmable gain instrumentation amplifier (pgia) that senses low-side or high-side battery current. ? pin programmable gain difference amplifier (pgda) that measures the terminal voltage of the battery. ? two loop filter error amplifiers that receive the battery target current and voltage and establish the dynamics of the constant current (cc) and constant voltage (cv) feedback loops. ? minimum output selector circuit that combines the outputs of the loop filter error amplifiers to perform automatic cc to cv switching. ? output clamp amplifier that drives the vctrl pin. the voltage range of this amplifier is bounded by the voltage at the vclp and vcln pins such that it cannot overrange the subsequent stage. the output clamp amplifier can drive switching and linear power converters. note that an increas- ing voltage at the vctrl pin must translate to a larger output current in the power converter. ? overcurrent and overvoltage comparators whose outputs are combined using a nor gate to drive the fault pin. the fault pin presents a logic low when either comparator is tripped. ? 2.5 v reference that can be used as the reference voltage for the overcurrent and overvoltage comparators. the output node of the 2.5 v reference is the vref pin. ? current sharing amplifier that detects the maximum battery current among several charging channels and whose output can be used to implement current balancing. ? logic input pin (mode) that changes the configuration of the controller from charge to discharge mode. a logic high at the mode pin configures charge mode; a logic low configures discharge mode. power supply connections the AD8450 requires two analog power supplies (avcc and avee), one digital power supply (dvcc), one analog ground (agnd), and one digital ground (dgnd). avcc and avee power all the analog blocks, including the pgia, pgda, op amps, and comparators. dvcc powers the mode input logic circuit and the fault output logic circuit. agnd provides a reference and return path for the 2.5 v reference, and dgnd provides a reference and return path for the digital circuitry. the rated absolute maximum value for avcc ? avee is 36 v, and the minimum operating avcc and avee voltages are +5 v and ?5 v, respectively. due to the high psrr of the AD8450 analog blocks, avcc can be connected directly to the high current power bus (the input voltage of the power converter) without risking the injection of supply noise to the controller outputs. a commonly used power supply combination is +25 v and ?5 v for avcc and avee, and +5 v for dvcc. the +25 v rail for avcc provides enough headroom to the pgia such that it can be connected in a high-side current sensing configuration with up to four batteries in series (4s). the ?5 v rail for avee allows the pgda to sense accidental reverse battery conditions (see the reverse battery conditions section). connect decoupling capacitors to all the supply pins. a 1 f capacitor in parallel with a 0.1 f capacitor is recommended. power supply sequencing ? as detailed in the absolute maximum ratings table (see table 2), the voltage at any input pin other than isvp, isvn, bvpx, and bvnx cannot exceed the positive analog supply (avcc) by more than 0.5 v and cannot be exceeded by the analog negative supply (avee) by 0.5v. additionally, supply and ground pins (dvcc, dgnd, and agnd) cannot exceed the positive analog supply (avcc) by more than 0.5 v and cannot be exceeded by the analog negative supply (avee) by 0.5v. therefore, power-on and power-off sequencing may be required to comply with the absolute maximum ratings. failure to comply with the absolute maximum ratings can result in functional failure or damage to the internal esd diodes. damaged esd diodes can cause parametric failures and cannot provide full esd protection, reducing reliability. power-on sequence to power on the device, take the following steps: 1. turn on avcc 2. tur n on avee 3. turn on dvcc 4. tur n on t he input sig na ls the positive analog supply (avcc) and the negative analog supply (avee) may be turned on simultaneously.
AD8450 data sheet rev. b | page 30 of 41 p ower - off s equence to power off the device, take the following steps: 1. turn of f the input signals . 2. turn o ff dvcc . 3. turn of f av ee . 4. turn of f avc c . the positive analog supply (avcc) and the negative analog supply (avee) may be turned off simultaneously. pgia connections for a description of the pgia, see the theory o f operati o n section, figure 49 , and figure 51 . the internal gains of the pgia (26, 66, 133, and 200) are selected by hardwiring the appropriate pin combinations (see table 5 ). table 5 . pgia gain connections pgia g ain connect rgp (pin 2) to connect rgn (pin 19) to 26 isgp0 (pin 4) isgn0 (pin 17) 66 isgp1 (pin 6) isgn1 (pin 15) 133 isgp2 (pin 8) isgn2 (pin 13) 200 isgp3 (pin 9) isgn3 (pin 12) if a di fferent gain value is desired, connect 10 k feedback resistors between the inverting inputs of the pgia preamplifiers (rgp and rgn pins) and the outputs of the pgia preamplifiers (rfbp and rfbn pins). also, connect a gain resistor (r g ) between the rgp and rgn pins. when using external resistors, the gain of the pgia is g ain = 2 (1 + 20 k?/ r g ) battery level shifter adp1972 pwm vctrl sense resistor isvp isvn bvpx bvnx avcc output drivers battery current avee cv buffer ? + ? + 1 vint buffer vsetbf vset iset c d c d c d vint ismea bvmea vve1 vve0 vvp0 ive1 ive0 ? + ? + ocps ocpr ovpr vref overcurrent comparator overvoltage comparator fault ovps output filter pgda ? + ? + pgia dc-to-dc power converter 1 set battery current set battery voltage AD8450 controller constant voltage loop filter amplifier cc and cv gates constant current loop filter amplifier mode switches (3) c = charge d = discharge 11966-059 external passive compensation network nor figure 59 . complete signal path of a battery test or formation system suitable for li - ion batteries
data sheet AD8450 rev. b | page 31 of 41 current sens ors t wo common options for current sens ors are isolated current sensing transducers and shunt resist ors . isolated current sensing transducers are galvanic al ly isolat ed from the power converter and are affected less by the high frequency noise generated by switch mode power supplies. s hunt resistors are less expensive and easier to deploy. if a shunt resistor sensor is used, a 4 - terminal , low resistance shunt resistor is recommended. two of the four terminals conduct the battery current , whereas the other two terminals conduct virtually no current . the terminals that conduct no current are sense terminals that are used to measure the voltage drop across the resistor (and, therefore, the current flowing through it) using an amplifier such as the pgia of the AD8450 . to interface the pgia with the current sensor, connect the sense terminals of the sensor to the isvp and isvn pins of the AD8450 (see figure 60). optional low - pass filter the AD8450 is designed to control both linear regulators and switching power converters. linear regulators are generally noise free, whereas switch mode p ower converters generate switching noise. connecting an external differential low - pass filter between the current sensor and the pgia inputs reduces the injection of switching noise into the pgia (see figure 60). 11966-060 isvp isvn + ? + rgn lpf rgp rgn isgpx isgnx 4-terminal shunt i bat ? ? + dut 20k 20k 10k 10k 10k 10k rfbp rfbn figure 60 . 4 - terminal shunt resistor connected to the current sense pgia pgda connections for a description of the pg d a, see the theory o f operatio n section , figure 49, and figure 52 . the internal gains of the pg d a ( 0.2 , 0.27 , 0.4 , and 0.8 ) are selected by connecting the appropriate input pair to the battery terminals (see table 6 ). table 6 . pgda gain connections pgda gain connect battery positive terminal to connect battery negative terminal to 0.8 bvp0 (pin 25 ) bvn0 (pin 31 ) 0.4 bvp1 (pin 24) bvn1 (pin 32) 0.27 bvp 2 (pin 23) bvn 2 (pin 33) 0.2 bvp 3 (pin 22) bvn 3 (pin 34) set t he pgda gain value to attenuate the voltage of up to four 5 v battery cells in series to a full - scale voltage of 4 v. for example, a 5 v battery voltage is attenuated to 4 v using the gain of 0.8, and a 20 v battery voltage (four 5 v batteries in series) is attenuated to 4 v using the gain of 0.2. this voltage scaling enables the use of a 5 v adc to read the battery voltage at the bvmea output pin. reverse battery conditions the output voltage of the AD8450 pgda can be used to detect a reverse battery connection. a ? 5 v rail for avee allows the output of the pgda to go below ground when the battery is connected backwa rd . t herefore , the condition can be detected by monitoring the bvmea pin for a negative voltage . battery current and voltage control inputs (iset and vset) the voltage s at the iset and vset input pins set the target battery current and voltage for the cons tant current (cc) and constant voltage (cv) loops. these inputs must be driven by a precision voltage source (or a dac connected to a precision reference) whose output voltage is referenced to the same voltage as the pgia and pgda reference pins (is refh/isrefl and bvrefh/bvrefl, respectively) . for example, if the pgia ref - erence pin s are connected to agnd, the voltage source connected to iset must also be referenced to agnd. in the same way , if the pgda reference pin s are connected to agnd, the volta ge source connected to vset must also be referenced to agnd. in constant current mode, when the cc feedback loop is in steady state, the iset input sets the battery current as follows: i bat_ss = s ia iset r g v is the pgia gain. r s is the value of the shunt resistor. in constant voltage mode, when the cv feedback loop is in steady state, the vset input sets the battery voltage as follows: v bat_ss = da vset g v where g da is the pgda gain. therefore, the accuracy and temperature stability of the formation and test system are dependent not only on the precision of the AD8450 , but also on the accuracy of the iset and vset inputs.
AD8450 data sheet rev. b | page 32 of 41 loop filter amplifie r s the AD8450 has two loop filter amplifiers , also known as error amplifiers (see figure 59 ). one amplifier is for constant current control (cc loop filter amplifier), and the other amplifier is for constant voltage control (cv loop filter amplifier). the outputs of these amplifiers are combined using a minimum output selector circuit to perform automatic cc to cv switching. table 7 lists the inputs of the loop filter amplifiers for charge mode and discharge mode. table 7 . integrator input connection s feedback loop function reference input feedback terminal control the current while discharging a battery is et ive0 control the current while charging a battery is et ive1 contr ol the voltage while discharging a battery v set vve0 control the voltage while charging a battery v set vve1 t he cc and cv amplifiers in charge mode and the cc amplifier in discharge mode are inverting integrators, whereas the cv amplifier in discharge mode is a noninverting integrator. there - fore, the cv am plifier in discharge mode uses an extra amplifier, the vset buffer , to buffer the vset input pin (see figure 49) . also, the cv amplifier in discharge m ode uses the vvp0 pin to couple the signal from the bvmea pin to the integrator. connectin g to a pwm controller ( vctrl pin ) the vctrl output pin of the AD8450 is designed to interface with linear power converters and with pulse - width modulation (pwm) controllers such as the adp1972 . the voltage range of the vctrl output pin is bounded by the voltages a t the vclp and vcln pins, as follows: v vcln ? 0.5 v < v vctrl < v vclp + 0.5 v because the maximum rated input voltage at the comp pin of the adp1972 is 5.5 v , connect th e clamp voltages of the output amplifier to +5 v (vclp) and ground (vcln) to prevent over - ranging of the comp input. as an additional prec aution, install an external 5.1 v z ener diode from the comp pin to ground with a series 1 k resistor connected between the vctrl and comp pins . consult the adp1972 data sheet for additional applications information. given the architecture of the AD8450 , the controller requires that an increasing voltage at the vctrl pin translate to a larger output current in the power converter. if this is not the case, a unity - gain inverting amplifier can be added in series with the AD8450 ou tput to add an extra inversion. overvoltage and over current comparators the reference inputs of the overvoltage and overcurrent comparators can be driven with external voltage references or with the internal 2.5 v reference (adjacent vref pin). if external voltage references are used, the sense inputs can be driven directly by the pgia and pgda output nodes, ismea and bvmea, respectively. if the internal 2.5 v reference is used, the sense inputs can be driven by resistor divi ders , which attenuate the voltage at the ismea and bvmea nodes. f or more information , see the overcurrent and overvoltage comparators section . step by step design example this section describes the systematic design of a 1 a battery charger/discharger using the ad8 450 controller and the adp1972 pulse - width modulation (pwm) controller. the power converter used in th is design is a nonisolated buck boost dc - to - dc converter. the target battery is a 4.2 v fully charged, 2.7 v fully discharged li - ion batter y. step 1: design the switching power converter select the switches and passive components of the buck boost power converter to support the 1 a maximum battery current. the design of the power converter is beyo nd the scope of this d ata sheet ; however, there are many application notes and other helpful documents available from manufacturers of integrated driver circuits and power mosfet output devices that can be used for reference. step 2: identify the control v oltage range of the adp1972 the control voltage range of the adp1972 (voltage range of the comp input pin) is 0.5 v to 4.5 v . an input voltage of 4.5 v results in the highest duty cycle and output current, wh ereas an input voltage of 0.5 v results in the lowest duty cycle and output current. because the comp pin connects directly to the vctrl output pin of the AD8450 , the battery current is proportional to the voltage at the vctrl pin . for information about how to interface the adp1972 to the power converter s witches, see the adp1972 data sheet. step 3: determine the control voltage for the cv loop and the pgda gain the relationship between the control voltage for the cv loop (the voltage at the vset pin), the target battery voltage , and the pgda gain is as follows: cv battery target voltage = gain pgda v vset in charge mode for a cv attery target oltage of 42 v the pgda gain of 08 maimies the dynamic range of the pgda therefore select a cv control oltage of 33 v in discharge mode for a cv attery target oltage of 2 v t h e cv control oltage is 21 v
data sheet AD8450 rev. b | page 33 of 41 step 4: determine the control voltage for the cc loop, the shunt res istor, and the pgia gain the relationship between the control voltage for the cc loop (the voltage at the iset pin ), the target battery current , and the pgia gain is as follows: cc battery target current = gain pgia r v s iset shunt resistor voltage = gain pgia v iset selecting the highest pgia gain of 200 reduces the oltage across the shunt resistor minimiing dissipated poer and inaccuracies due to self heating for a pgia gain of 200 and a target current of 1 a choosing a 20 m shunt resistor results in a control oltage of 4 v hen selecting a shunt resistor pay close attention to the resistor style and construction for lo poer applications many surface mount smd temperature st ale styles are aailale that solder to a mating pad on a printed circuit oard pcb for optimum accuracy specify a 4 terminal shunt resistor that proides separate high current and sense terminals t h i s type of resistor d irect s the maority of the at tery current through a high current path an additional pair of terminals proides a separate connection for the input leads to the pgia aoiding the poer loss inherent to forcing the full attery current through the distance to the pgia pins because th e ias current is so lo the sense error is significantly less than if the attery current ere to transerse the additional lead length step 5: choose the control voltage sources the input control voltages (the voltages at the iset and vset pins ) can be generated by an analog voltage source such as a vol tage reference or by a digital - to - a nalog converter (dac). in both cases, select a device that provides a stable , low noise output voltage. if a dac is preferred, analog devices offers a wide range of precision converters. for example, the ad5668 16- bit dac provides up to eight 0 v to 4 v sources when connected to an external 2 v reference. to maximize accuracy, the control voltage so urces must be referenced to the same potential as the outputs of the pgia and pgda . for example, if the pgia and pgda reference pins are connected to agnd, connect the reference pins of the control voltage sources to agnd. step 6: select the compensation d evices feedback controlled switching power converters require frequency compensation to guarantee loop stability. there are many refer - ences available about how to design the compensation for such power converters. the AD8450 provides active loop - filter error - amplifiers for the cc and cv control loops that can implement pi, pd, and pid compensators using external passive components. additional informati on a dditional information relative to using th e AD8450 is available in t he an - 1319 , compensator design for a battery charge/discharge unit using the AD8450 or the ad8451 .
AD8450 data sheet rev. b | page 34 of 41 evaluation board introduction figure 61 is a photograph of the AD8450 - e va l z . the evaluation board is a convenient standalone platform for evaluat ing the major elements of the AD8450 ( such as the pgia and pgda ) . the circuit architecture is particularly suitable for evaluating pid loop compensation when connected within a n operating charge/d ischarge system . four separate loop dynamic networks ar e available for constant current charge and discharge, and constant voltag e charge and discharge. the network sub circuits are s hown on the right hand side of the board schematic ( figure 62). sma connectors provide shielded access to the highly sensitive programmable gain instrumentation amplifier (pgia ) and the programmable gain differen ce amplifier (pgda ). sma connectors iset and vset are the constant current and constant voltage control inputs. the ismea and vctrl outputs, current and voltage alarm references , and trigger voltages are accessible for testing. the mode switch selects either the charge or discharge option. figure 62 is a schematic of the AD8450 - e va l z . table 8 lists and describes the various switches and their functions and lists the sma connector i/o . features and tests the AD8450 - e va l z contains many user friendly features to facilitate evaluat ion of the AD8450 performance. numerous connectors, test loops, and points facilitate the attach ment of scope probes and cables, and i/o switches conveniently exercise various device options . testing the AD8450 - evalz the schematic item abbreviation tp signifies a test loop. prior to testing, install jumpers tst1 through tst5 and move the shunts run1 through run5 to a single pin to open the connection. connect +25 v at avcc, ?5 v at avee, and +5 v at dvcc . pgia and offset pgia gain test apply 10 mv dc across tp isvp and tp isvn. for bench testing , connect isvn to ground using an external jumper. use the isgn switch to select the desired pgia gain option , and measure the output voltage at tpismea or tp imax (referenced to ground). for gains of 26, 66, 133, and 200, the output voltages are 260 mv, 660 mv, 1.33 v, and 2 v, respectively. s ubtract any residual offset voltages from the output reading before calculating the gain. 1 1966-061 figure 61 . photograph of the AD8450 - evalz
data sheet AD8450 rev. b | page 35 of 41 table 8 . AD8450 - evalz test switches and their functions switch function operation default position 1 isgn pgia g ain s witch the isgn switch selects one of four fixed gain values : 26, 66, 133 , or 200. user select bvgn pgda g ain s witch the bvgn switch selects one of four fixed gain values : 0. 2, 0 .27, 0 .4 , or 0. 8. n/a is_ref selects between offset options for the pgia norm: 0 v reference. norm 20mv: offsets the pgia reference by 20 mv. ext: an externally supplied reference voltage is applied to the pgia. bv_ref selects input source option for the bvrefh pin norm: overvoltage (ov) reference applied. norm 5mv: the bvda is offset by 5 mv. ext: an externally supplied reference voltage is applied to the bvda. mode selects charge or discharge mode the mode switch selects chg (logic high) or disch (logic low). chg run_test1 configures the iset and vset inputs to test the integrators. run: the iset and vset inputs are connected to sma connectors iset and vset. run test : connectors the iset and vset inputs to the 2.5 v reference. run_test2 configures the iset and vset outputs to test the integrators. run: configures the iset and vset outputs as integrators. run test: configures the iset and vset outputs as followers. 1 n/a means not applicable. table 9 . AD8450 - evalz sma connector functions connector function isvp input from the battery current sensor to the pgia positive input . isvn input from the battery current sensor to the pgia negative input . bvp input from the battery positive voltage terminal to the pgda positive input . bvn input from the battery negative voltage terminal to the pgda negative input . iset input to the AD8450 iset pin . vset input to the AD8450 vset pin . vctrl AD8450 control voltage output to the pwm or analog power supply comp input . cs_bu s AD8450 current sharing input/output bus . pgia in an application the differential inputs of the pgia assume the use of a high - side current shunt in series with the battery. to connect the eval uation board in an application, simply connect the isvp and isvn to the positive and negative shunt connections. be sure that both inputs are float ing (ungrounded). the isvp and i svn inputs tolerate the full a vcc common - mode vol tage applied to the board. simple offset t est s hort the pgia inputs from tpisvp to tpisvn to one of the black ground loops. the ismea output is 0 v the residual offset voltage multiplied by the gain . move the is _ ref switch to the 20 mv position to increase ismea by 20 m v. offset in an application in certain instances, the system operate s with various ground voltage levels. although the pgia is differential and floating, it may be advantageous to refer the pgia to a ground at or near the battery l oad. pg d a and offset simple test the pgda has four gain optio ns ( 0.8, 0.4, 0.27 , and 0.2 ) s e l ected with the four - position bvgn slide switch . set the b v_ ref switch to the norm position. t est t h e pgda amplifier in the same manner as pgia . apply 1 v dc between tpbvp and tpbvn . measure the output voltages at tp bvmea . the output voltages ar e 0.8 v, 0.4 v, 0.27 v , and 0.2 v , respec tively , at the four bvgn switch positions . pgda in an application for connection to an application, simply connect the input terminal across the battery. it is good practice to take advantage o f the differential input to achieve the most accurate measurements. pgda offset the bv_ref offset works just the same as the is_ref except that the fixed offset is 5 mv. simply use the bv_ref switch to select the option. for an external offset reference, move the bv_ref switch to ext and connect a wire from the tpbrefl and tpbrefh test loops to the desired reference points.
AD8450 data sheet rev. b | page 36 of 41 overload comparators the AD8450 features identical fault sensing comparators for overcurrent (ocps pin) and overvoltage (ovps pin) t o help protect against battery damage . the reference pins , ovpr and ocpr , are hardwired via 0 resistors , r 27 and r28 , to the 2.5 v reference. the outputs of the comparators are connected together internally , and are a ctive low in the event of an overdrive of either parameter . for reference, the sense pins are set at 20% greater than the reference. for other se nse voltage ratios, simply calculate a new value for the resistor divider. the 2.49 k resistor was selected as an easy equivalent to the 2.5 v reference , the 499 resistors to the i s mea and bvmea as 20% greater. these values were selected for an experimental 1 a charge/discharge system built in the lab. other ratios and values are user selected. as a basic test or experiment, simply apply enough voltage at the pgia or pgda inputs to exceed 3 v at i s mea or bvmea. the fault output pin switch es from 5 v to 0 v if either input exceeds the sense trigger level. vs et buffer the vset buffer is a unity gain , voltage follower pin accessible for testing . apply a v oltage up to 5 v at the vset input , and measure the output at tpvsetbf . cv and cc loop filter amplifier s the constant voltage (cv) and constant current (cc) integrators are identical circuits and are the two active integrator elements of the master loop compensation and switching block (see figure 49 ). except for their external connections, the two circuits are identical and are tested in the same way, sequentially . the integrator outputs are analog or ed together, creating the v ctrl output to the input of an external pulse - width modulation controller . as shown in figure 49 , the integrator op amp inputs are called i ve0, ive1, vve0, vve1, and vvp0. the first two letters ( iv or vv ) signif y the constant current or constant voltage integrator . the third letter identifies the noninverting input ( p ) or the inverting input ( e for error input) . the final digit (0 or 1) indicates the state of the mode circuit ( 0 for discharge and 1 for charge ) . because the integrators are connected in parallel, a static test of either integrator requires disabling the other by forcing the output to the supply rail, reverse bia sing the transistor/diode gate. cc and cv integrator test s the run _test1 and run_test2 switches provide all the circuit switching required to test the integrator. set run_test1 to the test position and apply 2.5 v to the iset and vset inputs ; then read 2.5 v at the vctrl output. set run_test2 to t est_cc , then test_cv , and the vctrl output voltage still measures 2.5 v. uncommitted op amp t he uncommitted op amp is configured as a follower ( r24 is installed between the oav n pin and the oav o pin ) . the input pin, oav p , is jumper connected to ground via oavp. to test t he uncommitted op amp, simply connect a jumper from tp 2.5v and pin 1 of jumper o av p. t h e output tpoavo read s 2.5 v. using the AD8450 except for the power converter and accessories, such as filters and current sensing, the AD8450 - e va l z includes all of the signal path elements necessary to implement a battery charging/ forming system (see figure 59). the AD8450 is usable with either linear or switch mode power converter s . switching converters typically generate higher noise levels than linear ; however, switching converters are the most popular by far because of significantly higher efficiency and lower cost. regardless of the power converter architecture used, the pid loop must be configured to reflect the phase shift and gain of the power stage. circuit simulation is helpful with this task. on the right hand side of figure 62 are four universal loop compensation circuits. all or part of the circuits are usable for installing fixed components when the AD8450 - e va l z is connected to a battery system for design verification. t here are two feedback amplifiers, but four p otentially distinctive separate configurations. the types and values of passive components vary according to the power converter and its characteristics. to us e the board f or setting up a charging system, replace the 10 k resistors in the feedback (there are no capacitors installed) and connect the measured feedback voltages by installing jumpers run1 thr o u gh run5. remove j umpers tst1 thr o u gh tst5 and install capacitors associated with the integrator .
data sheet AD8450 rev. b | page 37 of 41 schematic and artwor k 11966-062 tpisvp rgp ? 5 v bvp 3 s bvp 3 bvp 2 bvp 1 bvp 0 2 . 5 v cs cs _ bus tp _ imax isrefls bvn 3 s bvn 2 bvn 1 bvn 0 tp 2 . 5 v brefh brefl brefls gnd 5 gnd 4 gnd 3 gnd 2 gnd 1 gnd 8 drvovps dvccret 5 v + 5 v + isvp c 4 10 f 35 v + tpavee + isvn iset loop compensation field ( 5 ) aveeret avccret bvn 3 c 8 10 f 35 v c 7 10 f 35 v avcc ? 5 v ? 5 v dvcc 25 v b vn b vp ovps bvmea vref mode isvp rgp rgps isgp 1 isgp 0 s isgp 0 isgp 2 isgp 3 rfbp isgn 3 isgn 2 isgn 1 isgn 0 isgn 0 s rgns rgn isvn rfbn 17 18 15 16 8 7 6 5 4 3 2 14 13 9 12 11 10 19 1 20 49 44 43 41 50 46 45 47 48 42 vint n c n c n c 5 v ocps fault 37 34 36 35 28 27 26 30 33 32 31 29 rgps isgpos isgp 0 isgp 1 isgp 2 isgp 3 rfbp rfbn isgn 3 isgn 2 isgn 1 isgn 0 isgn 0 s rgns rgn tpisvn c 18 10 f 10 v g nd _ b vp g nd _ b vn 2 0 m v n o r m 26 66 133 200 26 66 133 200 0 . 4 0 . 27 0 . 2 0 . 8 0 . 4 0 . 27 0 . 2 0 . 8 r 24 0 isgp 1 s isgn 1 s isgp 1 s isgn 1 s c sh i s r e f h i m a x v r e f i s r e f ls i s r e f l o a v p i ve 1 i s m ea i ve 0 i s e t v i n t o a v o o a v n n c a g n d a v e e a v c c n c a v e e 2 . 5 v 6 5 2 1 7 4 9 8 1 0 3 6 5 2 1 7 4 9 8 1 0 3 AD8450 x1 gnd 6 gnd 7 t p ? 5 v tpbvmea 25 v c 21 1 f 50 v d i s ch tpvsetbf ismea c 9 0 . 1 f 50 v 51 5 v tpvctrl tpvclp 40 39 38 tpmode m o d e cv - discharge tp 49 tp 41 tp 61 tp 55 tp 14 tp 54 c 10 tbd dni c 14 tbd dni r 4 10 k r 1 0 cc - discharge i ve 0 tp 48 tp 40 c 3 tbd dni tp 1 tp 53 r 3 10 k tp 11 tp 13 c 6 tbd dni cc - charge vint t i v e 1 tp 58 tp 62 tp 43 tp 51 r 5 10 k r 6 0 c 11 tbd dni c 15 tbd dni tp 46 tp 57 tp 6 tp 3 tp 42 tp 50 tvve 1 tp 45 tp 18 tp 56 tp 19 c 24 tbd dni r 15 10 k c 17 tbd dni r 14 10 k tp 26 tp 25 r 12 0 tp 23 tp 24 tp 30 tp 33 c 23 tbd dni cv - charge bvmea vvp 0 tp 12 tp 4 r 13 10 k r 11 0 c 22 tbd dni r 2 10 k tp 36 tp 7 r 7 0 tp 8 tp 15 tp 9 tp 28 c 2 tbd dni tp 16 tp 37 tp 2 tp 5 tp 10 tp 29 c 1 tbd dni r 8 10 k tpvcln tp 32 tp 35 tp 39 tp 27 tp 59 tp 47 c 13 tbd dni tp 60 c 19 tbd dni r 9 10 k tp 52 tp 44 tp 63 ? 5 v vve 0 tp 17 tp 38 r 10 10 k tp 31 tp 34 c 12 tbd dni ismea vvp 0 bvmea 5 v c hg 2 vsetbf r 17 0 ? r 16 0 r 18 1 k cr 1 5 . 1 v 2 1 4 3 vint t v v e 1 v ve 1 6 8 5 7 run _ test 2 v ve 1 t v v e 1 r un t _ c c t _ c v r 27 0 r 28 0 c 19 10 f 10 v t p i s m ea tprgp tprgn 25 v c 5 1 0 f 1 0 v c 20 1 f 50 v ? 5 v c 25 0 . 1 f 50 v oavn r 22 0 t e s t r un 1 2 3 1 2 3 2 . 5 v r 20 1 k cr 3 5 . 1 v vset run _ test 1 tp _ vset tp _ iset r 29 2 . 49 k r 25 499 r 31 2 . 49 k r 30 499 ismea o a v o clmp _ vctrl tpvset 2 1 4 3 6 8 5 7 n o r m 5 m v bvdaref tpbrefh tpbrefl 1 3 ? i s g n ? i s g n isvn 80 64 62 69 65 68 67 73 71 78 74 77 76 79 66 75 72 70 61 63 r 21 0 d a r ef b v r ef ? b v g n ? b v g n bvrefh bvp 3 bvp 3 s bvrefl bvp 1 bvp 0 bvp 2 bvn 3 s bvrefls bvn 3 bvn 2 ovps bvmea bvn 1 bvn 0 vref agnd avee avcc mode 23 22 21 25 24 vctrl vcln vve 1 vint vclp vve 0 vvp 0 vset fault ocps ocpr ovpr vsetbf v r e f d g n d d v c c n c a v c c n c n c 59 54 56 53 58 55 57 52 60 vset r 19 1 k ? cr 2 5 . 1 v vset ocpr ovpr 2 1 4 3 6 8 5 7 tp _ isrefh tpisrefl 25 v e xt isiaref oavp iaref isrefl n c n c run 5 tst 5 tst 4 run 4 run 3 tst 3 vctrl run 2 tst 2 tst 1 run 1 e xt i s _ r ef tpbvp tpbvn tpoavp figure 62 . schematic of the AD8450 evaluation board
AD8450 data sheet rev. b | page 38 of 41 11966-063 figure 63. top silkscreen of the AD8450-evalz 11966-064 figure 64. AD8450-evalz primary side copper
data sheet AD8450 rev. b | page 39 of 41 11966-065 figure 65. AD8450-evalz secondary side copper 11966-066 figure 66. AD8450-evalz power plane
AD8450 data sheet rev. b | page 40 of 41 11966-067 figure 67. AD8450-evalz ground plane
data sheet AD8450 rev. b | page 41 of 41 outline dimensions compliant t o jedec s t andards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 t op view (pins down) pin 1 051706- a figure 68 . 80 - lead low profile quad flat package [ lqfp ] (st - 80 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD8450astz ? 40c to + 85c 80- lead low profile quad flat package [lqfp] st -80- 2 AD8450astz - rl ? 40c to + 85c 80- lead low profile quad flat package [lqfp] st -80- 2 AD8450 - evalz evaluation board 1 z = rohs compliant part. ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11966 - 0 - 8/ 15(b)

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